//******************************************************************/
//版本说明:
//V1.0		2011-11-05	jzhang	数码管接口，基于74HC595。输出时钟
//					15M，32位串移输出。
//******************************************************************/
module	out_ctrl(
			input	wire		sclk,
			input	wire		resetb,
			
			//输入显示数据控制
			input	wire	[3:0]	display_num_0,
			input	wire	[3:0]	display_num_1,
			input	wire	[3:0]	display_num_2,
			input	wire	[3:0]	display_num_3,
			input	wire		display_en,
			input	wire		led1,//SDRAN
			input	wire		led2,//phy
			input	wire		led3,//flash
			input	wire		led4,//hub
			
			//输出74HC595控制
			output	reg		shift_load,
			output	reg		shift_clk,
			output	reg		oe_1,
			output	reg		oe_2,
			output	reg		oe_3,
			output	reg		oe_4,
			output	reg		oe_5,
			//output	reg		oe_6,
			output	wire		shift_data
			);

parameter	Delay_Num	=8;

reg	[7:0]	out_num_0,out_num_1,out_num_2,out_num_3;
reg	[32+Delay_Num:0]	out_data;
reg	[2:0]	div_cnt;
reg	[5:0]	base_cnt;

//数码管显示数字
parameter 	Num_0	=8'b1100_0000;
parameter 	Num_1	=8'b1100_1111;
parameter 	Num_2	=8'b1010_0100;
parameter 	Num_3	=8'b1011_0000;
parameter 	Num_4	=8'b1001_1001;
parameter 	Num_5	=8'b1001_0010;
parameter 	Num_6	=8'b1000_0010;
parameter 	Num_7	=8'b1111_1000;			
parameter 	Num_8	=8'b1000_0000;	
parameter 	Num_9	=8'b1001_0000;	


always@(posedge sclk or negedge resetb)
	if(resetb==0)
		out_num_0<=0;
	else 
		case(display_num_0)
			0:		out_num_0<=	Num_0;
			1:		out_num_0<=	Num_1;
			2:		out_num_0<=	Num_2;
			3:		out_num_0<=	Num_3;
			4:		out_num_0<=	Num_4;
			5:		out_num_0<=	Num_5;
			6:		out_num_0<=	Num_6;
			7:		out_num_0<=	Num_7;
			8:		out_num_0<=	Num_8;
			9:		out_num_0<=	Num_9;
			default:	out_num_0<=	Num_0;
		endcase

always@(posedge sclk or negedge resetb)
	if(resetb==0)
		out_num_1<=0;
	else 
		case(display_num_1)
			0:		out_num_1<=	Num_0;
			1:		out_num_1<=	Num_1;
			2:		out_num_1<=	Num_2;
			3:		out_num_1<=	Num_3;
			4:		out_num_1<=	Num_4;
			5:		out_num_1<=	Num_5;
			6:		out_num_1<=	Num_6;
			7:		out_num_1<=	Num_7;
			8:		out_num_1<=	Num_8;
			9:		out_num_1<=	Num_9;
			default:	out_num_1<=	Num_0;
		endcase

always@(posedge sclk or negedge resetb)
	if(resetb==0)
		out_num_2<=0;
	else 
		case(display_num_2)
			0:		out_num_2<=	Num_0;
			1:		out_num_2<=	Num_1;
			2:		out_num_2<=	Num_2;
			3:		out_num_2<=	Num_3;
			4:		out_num_2<=	Num_4;
			5:		out_num_2<=	Num_5;
			6:		out_num_2<=	Num_6;
			7:		out_num_2<=	Num_7;
			8:		out_num_2<=	Num_8;
			9:		out_num_2<=	Num_9;
			default:	out_num_2<=	Num_0;
		endcase

always@(posedge sclk or negedge resetb)
	if(resetb==0)
		out_num_3<=0;
	else 
		case(display_num_3)
			0:		out_num_3<=	Num_0;
			1:		out_num_3<=	Num_1;
			2:		out_num_3<=	Num_2;
			3:		out_num_3<=	Num_3;
			4:		out_num_3<=	Num_4;
			5:		out_num_3<=	Num_5;
			6:		out_num_3<=	Num_6;
			7:		out_num_3<=	Num_7;
			8:		out_num_3<=	Num_8;
			9:		out_num_3<=	Num_9;
			default:	out_num_3<=	Num_0;
		endcase


always@(posedge sclk or negedge resetb)
	if(resetb==0)
		div_cnt<=0;
	else if(display_en==0)
		div_cnt<=0;
	else
		div_cnt<=div_cnt+1;

always@(posedge sclk or negedge resetb)
	if(resetb==0)
		base_cnt<=0;
	else if(display_en==0)
		base_cnt<=0;
	else if(div_cnt==7)begin
		if(base_cnt==36+Delay_Num)
			base_cnt<=0;
		else
			base_cnt<=base_cnt+1;
		end

always@(posedge sclk)
	if(display_en==0)
		shift_clk<=0;
	else if(base_cnt>=32+Delay_Num)
		shift_clk<=0;
	else if(div_cnt==3)
		shift_clk<=1;
	else if(div_cnt==7)
		shift_clk<=0;

always@(posedge sclk)
	if(base_cnt==34+Delay_Num)
		shift_load<=1;
	else
		shift_load<=0;

always@(posedge sclk)
	if(display_en==0)
		out_data<=0;
	else if(div_cnt==7)begin
		if(base_cnt==36+Delay_Num)
			out_data<={{led1,led2,led3,led4,4'b1111},out_num_3,out_num_2,out_num_1,out_num_0};
		else
			out_data<={out_data[31+Delay_Num:0],1'b0};
		end

assign	shift_data=out_data[31+Delay_Num];

always@(posedge sclk)
	if(display_en==0)
		begin
			oe_1<=1;		
			oe_2<=1;
			oe_3<=1;		
			oe_4<=0;
			oe_5<=1;
		end
	else if(base_cnt>=32+Delay_Num && base_cnt<=36+Delay_Num)
		begin
			oe_1<=1;		
			oe_2<=1;
			oe_3<=1;		
			oe_4<=0;
			oe_5<=1;
		end
	else
		begin
			oe_1<=0;		
			oe_2<=0;
			oe_3<=1;		
			oe_4<=0;
			oe_5<=0;
		end				
				
		
endmodule		
